CPU Instruction

Jun 21, 2023

• Instruction Level Parallelism

• mov
  • From memory to register, vice versa; Immediate to register or memory, register to register.
  • Move to register in 64bits, need movq
• add
• lea
  • leaq S, D : Move &S to D
    

See also Condition Code

• cmp
  • cmpq S1, S2
  • Based on S2 - S1, so jg means S2 > S1
• test
  • The test instructions behave in the same manner as the and instructions, except that they set the condition codes without altering their destinations.
• set
  • Used to access condition code
• jmp
  • It can be either a direct jump, where the jump target is encoded as part of the instruction, or an indirect jump, where the jump target is read from a register or a memory location.
    • jmp *%rax : direct
    • jmp *(%rax) : indirect
  • Use PC relative???? Addressing mode - Wikipedia
    • they encode the difference between the address of the target instruction and the address of the instruction immediately following the jump.
      

• Condition Code